Switch memory management using a linked list structure

ABSTRACT

A memory management method that has the steps of assigning pointers to free memory locations and linking the pointers to one another creating a linked list of free memory locations having a beginning and an end. A free head pointer is assigned to a memory location indicating the beginning of free memory locations and a free tail pointer is assigned to a memory location indicating the end of free memory locations. An initial data pointer is assigned to the memory location assigned to the free head pointer and an end of data pointer is assigned to a last data memory location. The free head pointer is assigned to a next memory location linked to the last data memory location assigned to the end of data pointer. The next memory location indicates the beginning of free memory locations.

REFERENCE TO RELATED APPLICATIONS

This is a Continuation of application Ser. No. 09/855,670, filed May 16,2001, which claims priority to U.S. Provisional Patent Application Ser.No. 60/237,764 filed on Oct. 3, 2000 and U.S. Provisional PatentApplication Ser. No. 60/242,701 filed on Oct. 25, 2000. The disclosureof the prior applications identified above are hereby incorporated byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates to a method and apparatus for high performanceswitching in local area communications networks such as token ring, ATM,ethernet, fast ethernet, and gigabit ethernet environments, generallyknown as LANs. In particular, the invention relates to a new switchingarchitecture geared to power efficient and cost sensitive markets, andwhich can be implemented on a semiconductor substrate such as a siliconchip.

2. Description of the Related Art

As computer performance has increased in recent years, the demands oncomputer networks has significantly increased; faster computerprocessors and higher memory capabilities need networks with highbandwidth capabilities to enable high speed transfer of significantamounts of data. The well-known ethernet technology, which is based uponnumerous IEEE ethernet standards, is one example of computer networkingtechnology which has been able to be modified and improved to remain aviable computing technology. A more complete discussion of prior artnetworking systems can be found, for example, in SWITCHED AND FASTETHERNET, by Breyer and Riley (Ziff-Davis, 1996), and numerous IEEEpublications relating to IEEE 802 standards. Based upon the Open SystemsInterconnect (OSI) 7-layer reference model, network capabilities havegrown through the development of repeaters, bridges, routers, and, morerecently, “switches”, which operate with various types of communicationmedia. Thickwire, thinwire, twisted pair, and optical fiber are examplesof media which has been used for computer networks. Switches, as theyrelate to computer networking and to ethernet, are hardware-baseddevices which control the flow of data packets or cells based upondestination address information which is available in each packet. Aproperly designed and implemented switch should be capable of receivinga packet and switching the packet to an appropriate output port at whatis referred to wirespeed or linespeed, which is the maximum speedcapability of the particular network. Basic ethernet wirespeed is up to10 megabits per second, and Fast Ethernet is up to 100 megabits persecond. A gigabit Ethernet is capable of transmitting data over anetwork at a rate of up to 1,000 megabits per second. As speed hasincreased, design constraints and design requirements have become moreand more complex with respect to following appropriate design andprotocol rules and providing a low cost, commercially viable solution.

Referring to the OSI 7-layer reference model discussed previously, thehigher layers typically have more information. Various types of productsare available for performing switching-related functions at variouslevels of the OSI model. Hubs or repeaters operate at layer one, andessentially copy and “broadcast” incoming data to a plurality of spokesof the hub. Layer two switching-related devices are typically referredto as multiport bridges, and are capable of bridging two separatenetworks. Bridges can build a table of forwarding rules based upon whichMAC (media access controller) addresses exist on which ports of thebridge, and pass packets which are destined for an address which islocated on an opposite side of the bridge. Bridges typically utilizewhat is known as the “spanning tree” algorithm to eliminate potentialdata loops; a data loop is a situation wherein a packet endlessly loopsin a network looking for a particular address. The spanning treealgorithm defines a protocol for preventing data loops. Layer threeswitches, sometimes referred to as routers, can forward packets basedupon the destination network address. Layer three switches are capableof learning addresses and maintaining tables thereof which correspond toport mappings. Processing speed for layer three switches can be improvedby utilizing specialized high performance hardware, and off loading thehost CPU so that instruction decisions do not delay packet forwarding.

SUMMARY OF THE INVENTION

The invention is directed to a scheme for reducing clock speed and powerconsumption in a network chip.

In one embodiment, the invention is a memory management method. Themethod has the steps of assigning pointers to free memory locations andlinking the pointers to one another creating a linked list of freememory locations having a beginning and an end. A free head pointer isassigned to a memory location indicating the beginning of free memorylocations and a free tail pointer is assigned to a memory locationindicating the end of free memory locations. An initial data pointer isassigned to the memory location assigned to the free head pointer and anend of data pointer is assigned to a last data memory location. The freehead pointer is assigned to a next memory location linked to the lastdata memory location assigned to the end of data pointer. The nextmemory location indicates the beginning of free memory locations.

In another embodiment, the invention is a memory management method. Themethod has the steps of assigning pointers to free memory locations andlinking the pointers to one another creating a linked list of freememory locations having a beginning and an end. A free head pointer isassigned to a memory location indicating the beginning of free memorylocations and a free tail pointer is assigned to a memory locationindicating the end of free memory locations. The memory locationassigned to the free tail pointer is linked to the memory locationassigned to an initial data pointer when memory locations occupied bydata is to be indicated as free memory. The free tail pointer isassigned to the last data memory location assigned to the end of datapointer.

Another embodiment of the invention is a memory management system. Thesystem has a pointer assignor that assigns pointers to free memorylocations and a linker that links said pointers to one another therebycreating a linked list of free memory locations having a beginning andan end. A free head pointer assignor assigns a free head pointer to amemory location indicating the beginning of free memory locations and afree tail pointer assignor assigns a free tail pointer to a memorylocation indicating the end of free memory locations. An initial datapointer assignor assigns an initial data pointer to the memory locationassigned to the free head pointer and an end of data pointer assignorassigns an end of data pointer to a last data memory location. The freehead pointer assignor assigns the free head pointer to a next memorylocation linked to the last data memory location assigned to said end ofdata pointer. The next memory location indicates the beginning of freememory locations.

The invention in another embodiment is a memory management system. Thesystem has a pointer assignor that assigns pointers to free memorylocations, and a linker that links the pointers to one another therebycreating a linked list of free memory locations having a beginning andan end. A free head pointer assignor assigns a free head pointer to amemory location indicating the beginning of free memory locations, and afree tail pointer assignor that assigns a free tail pointer to a memorylocation indicating the end of free memory locations. The linker linksthe memory location assigned to the free tail pointer to the memorylocation assigned to an initial data pointer when memory locationsoccupied by data is to be indicated as free memory and the free tailpointer assignor assigns the free tail pointer to the last data memorylocation assigned to said end of data pointer.

Another embodiment of the invention is a memory management system havinga pointer assignor means for assigning pointers to free memorylocations. A linker means links the pointers to one another therebycreating a linked list of free memory locations having a beginning andan end, and a free head pointer assignor assigns a free head pointer toa memory location indicating the beginning of the linked list of freememory locations. A free tail pointer assignor assigns a free tailpointer to a memory location indicating the end of the linked list offree memory locations, and an initial data pointer assignor means thatassigns an initial data pointer to the memory location assigned to thefree head pointer. An end of data pointer assignor means assigns an endof data pointer to a last data memory location. The free head pointerassignor means assigns the free head pointer to a next memory locationlinked to the last data memory location assigned to the end of datapointer, wherein the next memory location indicates the beginning offree memory locations.

In another embodiment, the invention is a memory management systemhaving a pointer assignor means for assigning pointers to free memorylocations and a linker means for linking the pointers to one anotherthereby creating a linked list of free memory locations having abeginning and an end. A free head pointer assignor means assigns a freehead pointer to a memory location indicating the beginning of the linkedlist of free memory locations, and a free tail pointer assignor meansassigns a free tail pointer to a memory location indicating the end ofthe linked list of free memory locations. The linker means links thememory location assigned to the free tail pointer to the memory locationassigned to an initial data pointer when memory locations occupied bydata is to be indicated as free memory. The free tail pointer assignormeans assigns the free tail pointer to the last data memory locationassigned to the end of data pointer.

The invention is in another embodiment a memory management device havinga pointer assignor that assigns pointers to free memory locations of amemory. The pointer assignor is in communication with the memory. Alinker links the pointers to one another thereby creating a linked listof free memory locations having a beginning and an end. The linker isalso in communication with the memory. A free head pointer assignorassigns a free head pointer to a memory location indicating thebeginning of the linked list of free memory locations. The free headpointer assignor is in communication with the memory. A free tailpointer assignor assigns a free tail pointer to a memory locationindicating the end of the linked list of free memory locations. The freetail pointer assignor is in communication with the memory. An initialdata packet pointer assignor assigns an initial data packet pointer tothe memory location assigned to the free head pointer. The initial datapacket pointer assignor is in communication with the memory. An end ofdata packet pointer assignor that assigns an end of data packet pointerto a last data memory location in the memory, and the end of data packetpointer assignor is in communication with the memory. The free headpointer assignor assigns the free head pointer to a next memory locationlinked to the last data packet memory location assigned to the end ofdata packet pointer, wherein the next memory location indicates saidbeginning of free memory locations.

In another embodiment, the invention is a memory management devicehaving a pointer assignor that assigns pointers to free memory locationsof a memory. The pointer assignor is in communication with the memory. Alinker links the pointers to one another thereby creating a linked listof free memory locations having a beginning and an end. The linker is incommunication with the memory. A free head pointer assignor assigns afree head pointer to a memory location indicating the beginning of thelinked list of free memory locations. The free head pointer assignor isalso in communication with the memory. A free tail pointer assignorassigns a free tail pointer to a memory location indicating the end ofthe linked list of free memory locations. The free tail pointer assignoris in communication with the memory. The linker links the memorylocation assigned to the free tail pointer to the memory locationassigned to an initial data pointer when memory locations occupied bydata is to be indicated as free memory, and the free tail pointerassignor assigns the free tail pointer to the last data memory locationassigned to the end of data pointer.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects and features of the invention will be more readilyunderstood with reference to the following description and the attacheddrawings, wherein:

FIG. 1 is a general block diagram of elements of the present invention;

FIG. 2 illustrates the data flow on the CPS channel of a network switchaccording to the present invention;

FIG. 3A illustrates a linked list structure of Packet Buffer Memory;

FIG. 3B illustrates a linked list structure of Packet Buffer Memory withtwo data packets;

FIG. 3C illustrates a linked list structure of Packet Buffer Memoryafter the memory occupied by one data packet is freed;

FIG. 3D illustrates a linked list structure of Packet Buffer Memoryafter the memory occupied by another data packet is freed;

FIG. 4A is a flow diagram of the steps to assign data to memorylocations in a linked list of free memory.

FIG. 4B is a flow diagram of the steps to add memory locationsdesignated for data to a linked list of free memory.

FIG. 5 is an illustration of a system for managing a linked list of freememory.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is an example of a block diagram of a switch 100 of the presentinvention. In this example, switch 100 has 12 ports, 102(1)-102(12),which can be fully integrated IEEE compliant ports. Each of these 12ports 102(1)-102(12) can be 10BASE-T/100BASE-TX/FX ports each having aphysical element (PHY), which can be compliant with IEEE standards. Eachof the ports 102(1)-102(12), in one example of the invention, has a portspeed that can be forced to a particular configuration or set so thatauto-negotiation will determine the optimal speed for each portindependently. Each PHY of each of the ports can be connected to atwisted-pair interface using TXOP/N and RXIP/N as transmit and receiveprotocols, or a fiber interface using FXOP/N and FXIP/N as transmit andreceive protocols.

Each of the ports 102(1)-102(12) has a Media Access Controller (MAC)connected to each corresponding PHY. In one example of the invention,each MAC is a fully compliant IEEE 802.3 MAC. Each MAC can operate at 10Mbps or 100 Mbps and supports both a full-duplex mode, which allows fordata transmission and reception simultaneously, and a half duplex mode,which allows data to be either transmitted or received, but not both atthe same time.

Flow control is provided by each of the MACs. When flow control isimplemented, the flow of incoming data packets is managed or controlledto reduce the chances of system resources being exhausted. Although thepresent embodiment can be a non-blocking, wire speed switch, the memoryspace available may limit data transmission speeds. For example, duringperiods of packet flooding (i.e. packet broadcast storms), the availablememory can be exhausted rather quickly. In order to enhance theoperability of the switch in these types of situations, the presentinvention can implement two different types of flow control. Infull-duplex mode, the present invention can, for example, implement theIEEE 802.3x flow control. In half-duplex mode, the present invention canimplement a collision backpressure scheme.

In one example of the present invention each port has a latency blockconnected to the MAC. Each of the latency blocks has transmit andreceive FIFOs which provide an interface to main packet memory. In thisexample, if a packet does not successfully transmit from one port toanother port within a preset time, the packet will be dropped from thetransmit queue.

In addition to ports 102(1)-102(12), a gigabit interface 104 can beprovided on switch 100. Gigabit interface 104 can support a GigabitMedia—Independent Interface (GMII) and a Ten Bit Interface (TBI). TheGMII can be fully compliant to IEEE 802.3ab. The GMII can pass data at arate of 8 bits every 8 ns resulting in a throughput of 2 Gbps includingboth transmit and receive data. In addition to the GMII, gigabitinterface 104 can be configured to be a TBI, which is compatible withmany industry standard fiber drivers. Since in some embodiments of theinvention the MDIO/MDC interfaces (optical interfaces) are notsupported, the gigabit PHY (physical layer) is set into the proper modeby the system designer.

Gigabit interface 104, like ports 102(1)-102(12), has a PHY, a GigabitMedia Access Controller (GMAC) and a latency block. The GMAC can be afully compliant IEEE 802.3z MAC operating at 1 Gbps full-duplex only andcan connect to a fully compliant GMII or TBI interface through the PHY.In this example, GMAC 108 provides full-duplex flow control mechanismsand a low cost stacking solution for either twisted pair or TBI modeusing in-band signaling for management. This low cost stacking solutionallows for a ring structure to connect each switch utilizing only onegigabit port.

A CPU interface 106 is provided on switch 100. In one example of thepresent invention, CPU interface 106 is an asynchronous 8 or 16 bit I/Odevice interface. Through this interface a CPU can read internalregisters, receive packets, transmit packets and allow for interrupts.CPU interface 106 also allows for a Spanning Tree Protocol to beimplemented. In one example of the present invention, a chip select pinis available allowing a single CPU control two switches. In this examplean interrupt pin when driven low (i.e., driven to the active state)requiring a pull-up resistor will allow multiple switches to becontrolled by a single CPU.

A switching fabric 108 is also located on switch 100 in one example ofthe present invention. Switching fabric 108 can allow for full wirespeed operation of all ports. A hybrid or virtual shared memory approachcan also be implemented to minimize bandwidth and memory requirements.This architecture allows for efficient and low latency transfer ofpackets through the switch and also supports address learning and agingfeatures, VLAN, port trunking and port mirroring.

Memory interfaces 110, 112 and 114 can be located on switch 100 andallow for the separation of data and control information. Packet buffermemory interface (PBM) 110 handles packet data storage while thetransmit queue memory interface (TXM) 112 keeps a list of packets to betransmitted and address table/control memory interface (ATM) 114 handlesthe address table and header information. Each of these interfaces canuse memory such as SSRAM that can be configured in various total amountsand chip sizes.

PBM 110 is located on switch 100 and can have an external packet buffermemory (not shown) that is used to store the packet during switchingoperations. In one example of the invention, packet buffer memory ismade up of multiple 256 byte buffers. Therefore, one packet may spanseveral buffers within memory. This structure allows for efficientmemory usage and minimizes bandwidth overhead. The packet buffer memorycan be configurable so that up to 4 Mbytes of memory per chip can beused for a total of 8 Mbytes per 24+2 ports. In this example, efficientmemory usage is maintained by allocating 256 byte blocks, which allowsstorage for up to 32K packets. PBM 110 can be 64 bits wide and can useeither a 64 bit wide memory or two 32 bit wide memories and can run at100 MHz.

TXM 112 is located on switch 100 and can have an external transmit queuememory (not shown). TXM 112, in this example, maintains 4 priorityqueues per port and allows for 64K packets per chip and up to 128Kpackets per system. TXM 112 can run at a speed of up to 100 MHz.

ATM 114 can be located on switch 100 and can have an external addresstable/control memory (not shown) used to store the address table andheader information corresponding to each 256 byte section of PBM 110.Address table/control memory allows up to 16K unique unicast addresses.The remaining available memory is used for control information. ATM 114,in this example, runs up to 133 MHz.

Switch 100, in one example of the invention, has a Flow Control Manager116 that manages the flow of packet data. As each port sends more andmore data to the switch, Flow Control Manager 116 can monitor the amountof memory being used by each port 102(1)-102(12) of switch 100 and theswitch as a whole. In this example, if one of the ports 102(1)-102(12)or the switch as a whole is using up too much memory as is predeterminedby a register setting predefined by the manufacturer or by a user, FlowControl Manager 116 will issue commands over the ATM Bus requesting theport or switch to slow down and may eventually drop packets ifnecessary.

In addition to Flow control manager 116, switch 100 also has a StartPoint Manager (SPM) 118 connected to Switching Fabric 108, a ForwardingManager (FM) 120 connected to Switching Fabric 108 and an AddressManager (AM) 122 connected to Switching Fabric 108.

Start Point Manager (SPM) 118, through Switching Fabric 108 in oneexample of the present invention, keeps track of which blocks of memoryin PBM 110 are being used and which blocks of memory are free.

Forwarding Manager 120 can, for example, forward packet data throughSwitching Fabric 108 to appropriate ports for transmission.

Address Manager (AM) 122 can, through Switching Fabric 108, manage theaddress table including learning source addresses, assigning headers topackets and keeping track of these addresses. In one example of theinvention, AM 122 uses aging to remove addresses from the address tablethat have not been used for a specified time period or after a sequenceof events.

An expansion port 124 can also be provided on switch 100 to connect twoswitches together. This will allow for full wire speed operation ontwenty-five 100M ports (includes one CPU port) and two gigabit ports.The expansion port 124, in this example, allows for 4.6 Gbps of data tobe transmitted between switches.

An LED controller 126 can also be provided on switch 100. LED controller126 activates appropriate LEDs to give a user necessary statusinformation. Each port of the ports 102(1)-102(12), in one example ofthe invention, has 4 separate LEDs, which provide per port statusinformation. The LEDs are fully programmable and are made up of portLEDs and other LEDs. Each LED can include a default state for each ofthe four port LEDs. An example of the default operation of each of theport LEDs are shown below. LED DEFAULT OPERATION 0 Speed Indicator OFF =10 Mbps or no link ON = 100 Mbps 1 Full/Half/Collision Duplex OFF = Theport is in half duplex or no link BLINK = The port is in half duplex anda collision has occurred ON = The port is in full duplex 2 Link/ActivityIndicator OFF = Indicates that the port does not have link BLINK = Linkis present and receive or transmit activity is occurring on the media ON= Link present without activity 3 Alert Condition OFF = No alertconditions, port is operating normally ON = The port has detected anisolate condition

In addition to the default operations for the port LEDs, each of theport LEDs can be programmed through registers. These registers can beset up, in one example of the invention, by a CPU. By havingprogrammable registers that control LEDs, full customization of thesystem architecture can be realized including the programmability of theblink rate.

Each of the LEDs can have a table, as shown below, associated with theLED, where register bits R_(Ax), R_(Bx) and R_(Cx) can be set to providea wide range of information.

For example, register bits R_(Ax), R_(Bx) and R_(Cx) can be set todetermine when LED_(ON), LED_(BLINK) and LED_(OFF) are activated ordeactivated. In addition to the port LEDs, there are additional LEDswhich indicate the status of the switch.

Registers 128 are located on switch 100 in this example of the presentinvention. Registers 128 are full registers that allow forconfiguration, status and Remote Monitoring (RMON) management. In thisexample, Registers 128 are arranged into groups and offsets. There are32 address groups each of which can contain up to 64 registers.

FIG. 2 is an illustration of one embodiment of the invention having aPBM Bus, an ATM Bus, and a TXM Bus for communications with otherportions of the switch. In this example PBM 110 is connected to the PBMBus and an external PBM Memory; TXM 112 is connected to the TXM Bus andan external TXM Memory; and ATM 114 is connected to the ATM Bus and anexternal ATM Memory. Each of the transmit (TX) and receive (RX) portionsof ports 102(1)-102(12) are connected to the PBM Bus, ATM Bus and TXMBus for communications.

FM 120 is connected to each of the ports 102(1)-102(12) directly and isalso connected to the ATM Bus for communications with other portions ofthe switch. SPM 118 and AM 122 are also connected to the ATM Bus forcommunications with other portions of the switch.

The operation of switch 100 for transmission of a unicast packet (i.e.,a packet destined for a single port for output) in one example of theinvention is made with reference to FIG. 2 as follows.

In this example, Switch 100 is initialized following the release of ahardware reset pin. A series of initialization steps will occurincluding the initialization of external buffer memory and the addresstable. All ports on the switch will then be disabled and the CPU willenable packet traffic by setting an enable register. As links becomeavailable on the ports (ports 102(1)-102(12) and gigabit port 104), anSPT protocol will confirm these ports and the ports will becomeactivated. After the initialization process is concluded normaloperation of Switch 100 can begin.

In this example, once a port has been initialized and activated, aPORT_ACTIVE command is issued by CPU. This indicates that the port isready to transmit and receive data packets. If for some reason a portgoes down or becomes disabled, a PORT_INACTIVE command is issued by theCPU.

During unicast transmission, a packet from an external source on port102(1) is received at the receive (RX) PHY of port 102(1).

In this example, the RX MAC of port 102(1) will not start processing thepacket until a Start of Frame Delimiter (SFD) for the packet isdetected. When the SFD is detected by the RX MAC portion of port 102(1),the RX MAC will place the packet into a receive (RX) FIFO of the latencyblock of port 102(1). As the RX FIFO becomes filled, port 102(1) willrequest an empty receive buffer from the SPM. Once access to the ATM Busis granted, the RX FIFO Latency block of port 102(1) sends packetsreceived in the RX FIFO to the external PBM Memory through the PBM Busand PBM 110 until the end of packet is reached.

The PBM Memory, in this example, is made up of 256 byte buffers.Therefore, one packet may span several buffers within the packet buffermemory if the packet size is greater than 256 bytes. Connections betweenpacket buffers can be maintained through a linked list system in oneexample of the present invention. A linked list system allows forefficient memory usage and minimized bandwidth overhead and will beexplained in further detail with relation to FIG. 3A-FIG. 3D.

At the same time packets are being sent to the external PBM Memory, theport will also send the source address to Address Manager (AM) 122 andrequest a filtering table from AM 122.

If the packet is “good”, as is determined through normal, standardprocedures known to those of ordinary skill in the art, such as validlength and IEEE standard packet checking such as a Cyclic RedundancyCheck, the port writes the header information to the ATM memory throughthe ATM Bus and ATM 114. AM 122 sends a RECEP_COMPL command over the ATMBus signifying that packet reception is complete. Other information isalso sent along with the RECEP_COMPL command such as the start addressand filtering table which indicates which ports the packet is to be sentout on. For example, a filtering table having a string such as“011111111111” would send the packet to all ports except port 1 andwould have a count of 11. The count simply is the number of ports thepacket is to be sent, as indicated by the number of “1”s.

Forwarding Manager (FM) 120 is constantly monitoring the ATM Bus todetermine if a RECEP_COMPL command has been issued. Once FM 120 hasdetermined that a RECEP_COMPL command has been issued, ForwardingManager (FM) 120 will use the filtering table to send packets toappropriate ports. It is noted that a packet will not be forwarded ifone of the following conditions is met:

-   -   a. The packet contains a CRC error    -   b. The PHY signals a receive error    -   c. The packet is less than 64 bytes    -   d. The packet is greater than 1518 bytes or 1522 bytes depending        on register settings    -   e. The packet is only forwarded to the receiving port

The RECEP_COMPL command includes information such as a filter table, astart pointer, priority information and other miscellaneous information.FM 120 will read the filter table to determine if the packet is to betransmitted from one of its ports. If it is determined that the packetis to be transmitted from one of its ports, FM 120 will send theRECEP_COMPL command information directly to the port. In this case, theRECEP_COMPL command information is sent to the TX FIFO of port 102(12).

If the port is busy, the RECEP_COMPL command information is transferredto TXM Memory through the TXM Bus and TXM 112. The TXM memory contains aqueue of packets to be transmitted. TXM Memory is allocated on a perport basis so that if there are ten ports there are ten queues withinthe TXM Memory allocated to each port. As each of the ports transmittersbecomes idle, each port will read the next RECEP_COMPL commandinformation stored in the TXM Memory. The TX FIFO of port 102(12) willreceive, as part of the RECEP_COMPL command information, a start pointerwhich will point to a header in ATM memory across the ATM Bus which inturn points to the location of a packet in the PBM Memory over the PBMBus. The port will at this point request to load the packet into thetransmit (TX) FIFO of port 102(12) and send it out through the MAC andPHY of port 102(12).

If the port is in half duplex mode, it is possible that a collisioncould occur and force the packet transmission to start over. If thisoccurs, the port simply re-requests the bus master and reloads thepacket and starts over again. If however, the number of consecutivecollisions becomes excessive, the packet will be dropped from thetransmission queue.

Once the port successfully transmits a packet, the port will signal FM120 that it is done with the current buffer. FM 120 will then decrementa counter which indicates how many more ports must transmit the packet.For example, if a packet is destined to eleven ports for output, thecounter, in this example, is set to 11. Each time a packet issuccessfully transmitted, FM 120 decrements the counter by one. When thecounter reaches zero this will indicate that all designated ports havesuccessfully transmitted the packet. FM 120 will then issue a FREEcommand over the ATM Bus indicating that the memory occupied by thepacket in the PBM Memory is no longer needed and can now be freed forother use.

When SPM 118 detects a FREE command over the ATM Bus, steps are taken toindicate that the space taken by the packet is now free memory.

Multicast and broadcast packets are handled exactly like unicast packetswith the exception that their filter tables will indicate that all ormost ports should transmit the packet. This will force the forwardingmanagers to transmit the packet out on all or most of their ports.

FIG. 3A is an illustration of a PBM Memory structure in one example ofthe invention. PBM Memory Structure 300 is a linked list of 256 bytesegments 302, 304, 306, 308, 310, 312, 314 and 316. In this examplesegment 302 is the free_head indicating the beginning of the free memorylinked list and segment 316 is the free_tail indicating the last segmentof free memory.

In FIG. 3B two packets have been received and stored in the PBM Memory.Packet 1 occupies segments 302, 306 and 308 and packet 2 occupiessegment 304. Segments 310, 312, 314 and 316 are free memory. Segment 310is the free_head indicating the beginning of free memory and segment 316is the free_tail indicating the end of free memory.

In FIG. 3C packet 1 has been fully transmitted and the ForwardingManager (FM) has issued a FREE command. Since packet 1 is already in alinked list format the SPM can add the memory occupied by packet 1 tothe free memory link list. The free_head, segment 310 remains the same.However, the free_tail is changed. This is accomplished by linkingsegment 316 to the beginning of packet 1, segment 302, and designatingthe last segment of packet 1, segment 308, as the free_tail. As aresult, there is a linked list starting with segment 310 linking tosegment 312, segment 312 linking to segment 314, segment 314 linking tosegment 316, segment 316 linking to segment 302, segment 302 linking tosegment 306 and segment 306 linking to segment 308 where segment 308 isthe free_tail.

FIG. 3D in this example simply illustrates the PBM Memory after packet 2has been transmitted successfully and the Forwarding Manager has issueda FREE command over the ATM Bus. The SPM will detect the FREE commandand then add the memory space occupied by packet 2 in the PBM Memory tothe free memory linked list. In this example segment 308 is linked tothe memory occupied by packet 2, segment 304, and segment 304 isidentified as the free_tail.

FIG. 4A is an illustration of the method steps taken in one embodimentof the invention. The steps are described in relation with FIGS. 3A-3D.In step 400, free memory locations 302, 304, 306, 308, 310, 312, 314 and316 are linked to one another forming a linked list of free memory. Inthe embodiment shown in FIG. 3A, memory location 302 has a pointerlinking memory location 302 to memory location 304. Likewise, memorylocation 304 has a pointer which links memory location 304 to memorylocation 306. As can be seen in FIG. 3A, the memory locations in thisembodiment of the invention are initially sequentially linked to oneanother where memory location 302 is linked to memory location 304,memory location 304 is linked to memory location 306, memory location306 is linked to memory location 308, etc.

In step 402, a free_head pointer is assigned to an initial memorylocation of the linked list of free memory. As can be seen in theexample illustrated in FIG. 3A, the free_head pointer is assigned tomemory location 302.

In step 404, a free tail pointer is assigned to a last memory locationof the linked list. In the example illustrated in FIG. 3A, the free tailis assigned to memory location 316, which in this case is the lastmemory location of the linked list of free memory.

In step 406, an initial data pointer is assigned to the memory locationassigned to the free head pointer. For example, referring back to FIG.3A, if a first packet of data were to be saved, the initial data pointerwould be assigned to memory location 302 where the free head pointer wasassigned. In step 408, the next memory location linked to the memorylocation assigned to the initial data pointer would be assigned to storemore data. For example, if the data would require free memory locations,memory locations 304 and 306 would also be assigned to data packet 1. Atmemory location 306, an end of data pointer would be assigned to thislast data location. The free head pointer would then be assigned tomemory location 308 indicating the beginning of free memory as describedin step 414.

In another example illustrated in FIG. 3B, a free head pointer initiallypoints to memory location 302 and packet 2 occupies memory location 304.When data packet 1 is to be saved, the initial data pointer is assignedto memory location 302. In this example, packet 1 needs three memorylocations and in this case, memory location 306 was linked to memorylocation 302 and memory location 308 was linked to memory location 306.Thus, the data pointers for packet 1 are assigned to memory locations302, 306 and 308. The end of data pointer is assigned to memory location308.

In step 414, the free head pointer is assigned to the next memorylocation linked to the last data memory location 308, which is in thiscase, memory location 310. Therefore, the free head pointer is assignedto memory location 310 and the free tail pointer is maintained as memorylocation 316.

FIG. 4B illustrates the method steps in one embodiment of the inventionfor freeing memory taken up by data packets and adding this memory tothe linked list of free memory.

In step 416, the memory location assigned to the initial data pointer islinked to the memory location assigned to the free tail pointer. Forexample, in FIG. 3C, packet 1 previously occupied memory locations 302,306 and 308. In this case, the free tail pointer was assigned to memorylocation 316. In accordance with step 416 as described in FIG. 4B, thememory location assigned to the free tail pointer 316 is linked to thememory location assigned to the initial data pointer, memory location302.

In step 418, the free tail pointer is assigned to the memory locationassigned to the end of data pointer. For example, in FIG. 3C, the end ofdata pointer for packet 1 was memory location 308. In this example, thefree tail pointer is assigned to the memory location assigned to the endof data pointer, memory location 308. The free head pointer in thisexample remains assigned to memory location 310.

In FIG. 3D, packet 2 is indicated as being free memory. Thus, inaccordance with step 416, the memory location 308 assigned to the freetail is linked to the initial data pointer memory location 304. Sincedata packet 2 only occupies one memory location, the end of data pointeris also assigned to memory location 304.

In step 418, the free tail pointer is assigned to the memory locationassigned to the end of data pointer. In the example depicted in FIG. 3D,the free tail pointer is assigned to memory location 304 which wasassigned to the end of data pointer.

FIG. 5 is an illustration of a system for managing a linked list memory.FIG. 5 will be described with reference to FIGS. 3A-3D. A pointerassigner 500 is responsible for linking memory locations to one anotheras depicted in FIG. 3A. For example, in this example, pointers areassigned to memory locations 302, 304, and 306-316.

Linker 502 directs which pointers are assigned to which memorylocations. For example, in FIG. 3A, the pointer of memory location 302is linked to memory location 304. The memory location 304 is linked tomemory location 306. The memory location 306 is linked to memorylocation 308, etc.

The system also has a free head pointer assignor 504 and a free tailpointer assignor 506. The free head pointer assignor 504 assigns a freehead pointer to the beginning of a linked list structure. In this case,the free head pointer assignor assigns a free head pointer to memorylocation 302 as depicted in FIG. 3A. The free tail pointer 506 assigns afree tail pointer to the last m memory location of the linked list asdepicted in FIG. 3A. In this case, the free tail pointer assignorassigns the free tail pointer to memory location 316.

The system also has a initial data pointer assignor 408 which assigns aninitial data pointer to the memory location the free head pointer isassigned to. For example, in FIG. 3B, packet 2 occupied memory location304 and the free head pointer was assigned to memory location 302. Theinitial data pointer assignor 508 assigned the initial data pointer tomemory location 302.

Data assignor 510 assigns a sufficient number of memory locations tostore data packets until an end of data has been found. In this case,data packet 1 needs three memory locations. Therefore, the data assignorassigns the packet data to memory locations 306 and 308.

The end of data pointer assignor 512 determines when the end of data hasbeen reached and assigns an end of data pointer to the memory locationoccupied by the end of data. In this case, the end of data pointerassignor 512 assigns an end of data pointer to memory location 308indicating the end of data as shown in FIG. 3B.

The free head pointer assignor 504 then reassigns the free head to thenext memory location in the linked list of memory assigned to the memorylocation the end of data pointer assignor the end of data pointer isassigned to. In this case, the end of data pointer is assigned to memorylocation 308. Therefore, this free head pointer is assigned to the nextmemory location in the linked list, memory location 310.

In the case that memory is to be freed, as illustrated in FIG. 3C,linker 502 links the memory location that the free tail pointer waspointing to the memory location the initial data pointer was assigned.In this case, as illustrated in FIG. 3C, the free tail pointer wasinitially assigned to memory location 316 and the initial data pointerwas assigned to memory location 302. Therefore, memory location 316 islinked to memory location 302 by linker 502. Finally, in order toindicate the memory location occupied by packet 1 as free memory, thefree tail pointer assignor 506 assigns the memory location assigned tothe end of data pointer memory location 308 to free tail pointer. Thus,the free tail pointer is assigned to memory location 308.

The above-discussed configuration of the invention is, in a preferredembodiment, embodied on a semiconductor substrate, such as silicon, withappropriate semiconductor manufacturing techniques and based upon acircuit layout which would, based upon the embodiments discussed above,be apparent to those skilled in the art. A person of skill in the artwith respect to semiconductor design and manufacturing would be able toimplement the various modules, interfaces, and tables, buffers, etc. ofthe present invention onto a single semiconductor substrate, based uponthe architectural description discussed above. It would also be withinthe scope of the invention to implement the disclosed elements of theinvention in discrete electronic components, thereby taking advantage ofthe functional aspects of the invention without maximizing theadvantages through the use of a single semiconductor substrate.

Although the invention has been described based upon these preferredembodiments, it would be apparent to those of skilled in the art thatcertain modifications, variations, and alternative constructions wouldbe apparent, while remaining within the spirit and scope of theinvention. In order to determine the metes and bounds of the invention,therefore, reference should be made to the appended claims.

1. A memory management method comprising the steps of: assigningpointers to free memory locations; linking said pointers to one anothercreating a linked list of free memory locations having a beginning andan end; assigning a free head pointer to a memory location indicatingsaid beginning of free memory locations; assigning a free tail pointerto a memory location indicating said end of free memory locations;assigning an initial data pointer to said memory location assigned tosaid free head pointer; assigning an end of data pointer to a last datamemory location; assigning said free head pointer to a next memorylocation linked to said last data memory location assigned to said endof data pointer, wherein said next memory location indicates saidbeginning of free memory locations.
 2. The method as recited in claim 1wherein when data to be saved is only large enough to occupy one memorylocation said end of data pointer is assigned to said memory locationassigned to said initial data pointer.
 3. The method as recited in claim1 wherein when data to be saved is larger than one memory location themethod comprises the steps of: assigning a sufficient number of memorylocations linked to said memory location assigned to said initial datapointer.
 4. The method as recited in claim 1 further comprising thesteps of: linking said memory location assigned to said free tailpointer to said memory location assigned to said initial data pointerwhen said data is to be indicated as free memory; and assigning saidfree tail pointer to said last data memory location assigned to said endof data pointer.
 5. A memory management method comprising the steps of:assigning pointers to free memory locations; linking said pointers toone another creating a linked list of free memory locations; assigning afree head pointer to a memory location indicating said beginning of freememory locations; assigning a free tail pointer to a memory locationindicating said end of free memory locations; and linking said memorylocation assigned to said free tail pointer to said memory locationassigned to an initial data pointer when memory locations occupied bydata is to be indicated as free memory.
 6. The method as recited inclaim 5 further comprising the steps of: assigning an initial datapointer to said memory location assigned to said free head pointer;assigning an end of data pointer to a last data memory location;assigning said free head pointer to a next memory location linked tosaid last data memory location assigned to said end of data pointer,wherein said next memory location indicates said beginning of freememory locations.
 7. The method as recited in claim 6 wherein when datato be saved is only large enough to occupy one memory location said endof data pointer is assigned to said memory location assigned to saidinitial data pointer.
 8. The method as recited in claim 6 wherein whendata to be saved is larger than one memory location the method comprisesthe steps of: assigning a sufficient number of memory locations linkedto said memory location assigned to said initial data pointer.
 9. Amemory management system comprising: a pointer assignor that assignspointers to free memory locations; a linker that links said pointers toone another thereby creating a linked list of free memory locationshaving a beginning and an end; a free head pointer assignor that assignsa free head pointer to a memory location indicating said beginning ofsaid linked list of free memory locations; a free tail pointer assignorthat assigns a free tail pointer to a memory location indicating saidend of said linked list of free memory locations; an initial datapointer assignor that assigns an initial data pointer to said memorylocation assigned to said free head pointer; and an end of data pointerassignor that assigns an end of data pointer to a last data memorylocation; wherein said free head pointer assignor assigns said free headpointer to a next memory location linked to said last data memorylocation assigned to said end of data pointer, wherein said next memorylocation indicates said beginning of free memory locations.
 10. Thesystem as recited in claim 9 wherein when data to be saved is only largeenough to occupy one memory location said end of data pointer assignorassigns said end of data pointer to said memory location assigned tosaid initial data pointer.
 11. The system as recited in claim 9 whereinwhen data to be saved is larger than one memory location the systemfurther comprises: a data assignor that assigns a sufficient number ofmemory locations linked to said memory location assigned to said initialdata pointer.
 12. The system as recited in claim 9 wherein said linkerlinks said memory location assigned to said free tail pointer to saidmemory location assigned to said initial data pointer when said data isto be indicated as free memory; and said assignor assigns said free tailpointer to said last data memory location assigned to said end of datapointer.
 13. A memory management system comprising: a pointer assignorthat assigns pointers to free memory locations; a linker that links saidpointers to one another thereby creating a linked list of free memorylocations; a free head pointer assignor that assigns a free head pointerto a memory location indicating said beginning of said linked list offree memory locations; and a free tail pointer assignor that assigns afree tail pointer to a memory location indicating said end of saidlinked list of free memory locations; and wherein said linker links saidmemory location assigned to said free tail pointer to said memorylocation assigned to an initial data pointer when memory locationsoccupied by data is to be indicated as free memory.
 14. The system asrecited in claim 13 further comprising: an initial data pointer assignorthat assigns an initial data pointer to said memory location assigned tosaid free head pointer; and an end of data pointer assignor that assignsan end of data pointer to a last data memory location; wherein said freehead pointer assignor assigns said free head pointer to a next memorylocation linked to said last data memory location assigned to said endof data pointer, wherein said next memory location indicates saidbeginning of free memory locations.
 15. The system as recited in claim14 wherein when data to be saved is only large enough to occupy onememory location said end of data pointer assignor assigns said end ofdata pointer to said memory location assigned to said initial datapointer.
 16. The system as recited in claim 14 wherein when data to besaved is larger than one memory location, a data assignor assigns asufficient number of memory locations linked to said memory locationassigned to said initial data pointer.
 17. A memory management systemcomprising: a pointer assignor means for assigning pointers to freememory locations; a linker means for linking said pointers to oneanother thereby creating a linked list of free memory locations having abeginning and an end; a free head pointer assignor means for assigning afree head pointer to a memory location indicating said beginning of saidlinked list of free memory locations; a free tail pointer assignor meansfor assigning a free tail pointer to a memory location indicating saidend of said linked list of free memory locations; an initial datapointer assignor means for assigning an initial data pointer to saidmemory location assigned to said free head pointer; and an end of datapointer assignor means for assigning an end of data pointer to a lastdata memory location; wherein said free head pointer assignor meansassigns said free head pointer to a next memory location linked to saidlast data memory location assigned to said end of data pointer, whereinsaid next memory location indicates said beginning of free memorylocations.
 18. The system as recited in claim 17 wherein when data to besaved is only large enough to occupy one memory location said end ofdata pointer assignor means assigns said end of data pointer to saidmemory location assigned to said initial data pointer.
 19. The system asrecited in claim 17 wherein when data to be saved is larger than onememory location the system further comprises: a data assignor means forassigning a sufficient number of memory locations linked to said memorylocation assigned to said initial data pointer.
 20. The system asrecited in claim 17 wherein said linker means links said memory locationassigned to said free tail pointer to said memory location assigned tosaid initial data pointer when said data is to be indicated as freememory; and said assignor means assigns said free tail pointer to saidlast data memory location assigned to said end of data pointer.
 21. Amemory management system comprising: a pointer assignor means forassigning pointers to free memory locations; a linker means for linkingsaid pointers to one another thereby creating a linked list of freememory locations; a free head pointer assignor means for assigning afree head pointer to a memory location indicating said beginning of saidlinked list of free memory locations; and a free tail pointer assignormeans for assigning a free tail pointer to a memory location indicatingsaid end of said linked list of free memory locations; and wherein saidlinker means links said memory location assigned to said free tailpointer to said memory location assigned to an initial data pointer whenmemory locations occupied by data is to be indicated as free memory. 22.The system as recited in claim 21 further comprising: an initial datapointer assignor means for assigning an initial data pointer to saidmemory location assigned to said free head pointer; and an end of datapointer assignor means for assigning an end of data pointer to a lastdata memory location; wherein said free head pointer assignor meansassigns said free head pointer to a next memory location linked to saidlast data memory location assigned to said end of data pointer, whereinsaid next memory location indicates said beginning of free memorylocations.
 23. The system as recited in claim 22 wherein when data to besaved is only large enough to occupy one memory location said end ofdata pointer assignor means assigns said end of data pointer to saidmemory location assigned to said initial data pointer.
 24. The system asrecited in claim 22 wherein when data to be saved is larger than onememory location, a data assignor means assigns a sufficient number ofmemory locations linked to said memory location assigned to said initialdata pointer.
 25. A memory management device comprising: a pointerassignor that assigns pointers to free memory locations of a memory,said pointer assignor in communication with said memory; a linker thatlinks said pointers to one another thereby creating a linked list offree memory locations having a beginning and an end, said linker incommunication with said memory; a free head pointer assignor thatassigns a free head pointer to a memory location indicating saidbeginning of said linked list of free memory locations, said free headpointer assignor in communication with said memory; a free tail pointerassignor that assigns a free tail pointer to a memory locationindicating said end of said linked list of free memory locations, saidfree tail pointer assignor in communication with said memory; an initialdata packet pointer assignor that assigns an initial data packet pointerto said memory location assigned to said free head pointer, said initialdata packet pointer assignor in communication with said memory; and anend of data packet pointer assignor that assigns an end of data packetpointer to a last data memory location in said memory, said end of datapacket pointer assignor in communication with said memory; wherein saidfree head pointer assignor assigns said free head pointer to a nextmemory location linked to said last data packet memory location assignedto said end of data packet pointer, wherein said next memory locationindicates said beginning of free memory locations.
 26. The device asrecited in claim 25 wherein when a single data packet is to be savedsaid end of data packet pointer assignor assigns said end of data packetpointer to said memory location assigned to said initial data packetpointer.
 27. The device as recited in claim 25 wherein the devicefurther comprises: a data packet assignor that assigns a sufficientnumber of memory locations linked to said memory location assigned tosaid initial data packet pointer, said data packet assignor incommunication with said memory.
 28. The device as recited in claim 25wherein said linker links said memory location assigned to said freetail pointer to said memory location assigned to said initial datapacket pointer when said data packet is to be indicated as free memory;and said assignor assigns said free tail pointer to said last datapacket memory location assigned to said end of data packet pointer. 29.A memory management device comprising: a pointer assignor that assignspointers to free memory locations of a memory; a linker that links saidpointers to one another thereby creating a linked list of free memorylocations; a free head pointer assignor that assigns a free head pointerto a memory location indicating said beginning of said linked list offree memory locations; and a free tail pointer assignor that assigns afree tail pointer to a memory location indicating said end of saidlinked list of free memory locations; wherein said linker links saidmemory location assigned to said free tail pointer to said memorylocation assigned to an initial data pointer when memory locationsoccupied by data is to be indicated as free memory.
 30. The device asrecited in claim 29 further comprising: an initial data packet pointerassignor that assigns an initial data packet pointer to said memorylocation assigned to said free head pointer, said initial data packetpointer assignor in communication with said memory; and an end of datapacket pointer assignor that assigns an end of data packet pointer to alast data packet memory location, said end of data packet pointerassignor in communication with said memory; wherein said free headpointer assignor assigns said free head pointer to a next memorylocation linked to said last data packet memory location assigned tosaid end of data packet pointer, wherein said next memory locationindicates said beginning of free memory locations.
 31. The device asrecited in claim 30 wherein when a single data packet is to be savedsaid end of data packet pointer assignor assigns said end of data packetpointer to said memory location assigned to said initial data packetpointer.
 32. The device as recited in claim 30 wherein when more thanone data packet is to be saved, a data packet assignor assigns asufficient number of memory locations linked to said memory locationassigned to said initial data packet pointer, said data packet assignorin communication with said memory.